In electronic circuits, noise becomes an ever more limiting consideration as dynamic range increases and/or as minimum detectable signal decreases. One particular source of noise in a mixed digital and analog signal application is the effect on critical analog signal paths of the various digital signals (data and clocks). One commonly used such critical analog signal path is the switching or steering of analog reference signals by control elements, which are themselves activated by digital control signals. In a physically realizable system, it is impossible to completely isolate these digital control signals from the analog signals they are controlling because of coupling through the analog signal control elements, and also because digital circuits consume time-varying power and cause time-varying loading, IR drops, and charge injection, which in turn causes interactions with the overall signal processing circuit. These effects cause changes in reference signals, supply voltages, bias levels, clocking phases, transition phases, and substrate effects that in turn corrupt the desired analog signal being processed. Because of inevitable parasitics and non-ideal circuits, this can cause data dependant loading and spurious coupled signal modulation. In this manner the digital signals add noise and/or distortion to the analog signals.
One example of a signal processing circuit in which such considerations are relevant is a current steering digital-to-analog converter (DAC), which converts a digital data stream input into a corresponding analog signal output. FIG. 1 shows a portion of a typical one-bit current steering DAC cell 100 in which a digital data stream is applied to a synchronous digital output latch 101. In real world applications, considerable digital processing is involved in producing such a digital data stream, but in the context of a DAC, such preceding digital circuitry need not be described. When the latch 101 is clocked, the data present on the D-input is transferred to the Q output, and its complement is transferred to the Q-bar output. For multi-bit systems, multiple cells 100 are arranged in parallel so as to share a common output terminal arrangement.
The outputs of latch 101 control switch drivers 102, which in turn operate differential switch pair 103 that control a constant current source supplied from a common source node. For a given logic state present on the output of the latch 101, one switch of the switch pair 103 will be on, and the other will be off. When the logic state on the output latch 101 changes, the on-off states of the switches in switch pair 103 also change correspondingly. Whichever switch of the switch pair 103 is on provides a current path for a constant current source 104 through one of the analog output resistors 105 (which typically are part of a separate client application). Thus, an analog signal output signal is developed at output terminals 106.
In theory, such a current steering DAC 100 can operate at any frequency to provide an analog output corresponding to the digital data input. In the real world, errors and noise occur throughout the system, the effects of which increase with operating frequency. These effects may be code dependent and may result in distortion in the analog output signal.
One approach to reducing code dependent noise is presented by FIG. 8 of U.S. Pat. No. 6,344,816, which describes adding an additional clocked circuit called a “dummy latch” in parallel with the output latch 101. The output of the dummy latch is not itself used in any way, rather the dummy latch and the output latch 101 are connected and operated such that with every cycle of the clocking signal, one of the latches will change state and the other will not. Thus, if the output latch 101 changes state with the data signal, the dummy latch maintains its logic state, and if the output latch 101 maintains its logic state constant with an unchanging data signal then the dummy latch will change logic states. According to the '816 patent, this arrangement maintains a constant loading on the clocking signal that is independent of the data signal logic state. There is no suggestion in the '816 that its teaching might be extensible beyond its focus on the clocking signal.